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Core1553BRT v4.0 Handbook
Table 3-5 ? Backend Signals (continued)
Port Name
Type
Description
MEMCEN
MEMDEN
Out Control Signal Enable (active high). This signal is HIGH when the core is
requesting the memory bus and has been granted control. It is intended to
enable any tristate drivers that may be implemented on the memory control and
address lines.
Out Data Bus Enable (active high). This signal is HIGH when the core is requesting
the memory bus, has been granted control, and is waiting to write data. It is
intended to enable any bidirectional drivers that may be implemented on the
memory data bus.
Note: *The 10 μs refers to the time from MEMREQn being asserted to the core deasserting its
MEMREQn signal. The core has an internal overhead of five clock cycles, and any inserted wait
cycles will also reduce this time. This time increases to 19.5 μs if the WRTTSW and WRTCMD
inputs are LOW.
Standard Memory Address Map
Core1553BRT requires an external 2,048×16 memory device. This memory is split into sixty-four 32-
word data buffers. Each of the 30 subaddresses has a receive and a transmit buffer, as shown in
The memory allocated to the unused receive subaddresses 0 and 31 is used to provide status
information back to the rest of the system. At the end of every transfer, a TSW is written to these
locations.
Table 3-6 ? Standard Memory Address Map
Address
000–01F
020–03F
...
3C0–3DF
3E0–3FF
400–41F
420–43F
...
RAM Contents
RX transfer status words
Receive subaddress 1
...
Receive subaddress 30
TX transfer status words
Not used
TX transfer subaddress 1
...
Action
The core only writes to these addresses (except when
SA30LOOP is HIGH).
The core only reads from these addresses.
7C0–7DF TX transfer subaddress 30
7E0–7FF
Not used
Revision 3
19
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